1. Field of the Invention
The invention relates generally to a RAM memory circuit and relates more particularly to devices for sampling the data which are received at the memory circuit.
2. Description of the Related Art
As is known, the acronym RAM stands for Random Access Memory (a read/write memory having direct and random access to the memory cells). Synchronous dynamic RAMs (so-called SDRAMs), particularly those which operate at a “multiplied data rate”, as are increasingly being used, for example, as main memories in PCs, are a preferred but not exclusive field of application of the invention.
RAMs are usually operated in conjunction with a controller which provides the RAM with the data which are to be written and receives the data which have been read from the RAM. The controller also provides the address information for selecting those memory cells in the RAM which are to be written to or read from, and also commands for the operating sequences in the RAM. In the case of synchronous RAMs, the controller also provides a system clock signal which is used to synchronize the transmission of addresses and commands and to clock the operations of reading from, and writing to, the memory cells.
The digital data are usually transmitted between a RAM and the associated controller in the form of so-called “bursts” which each comprise a sequence of individual bits or a sequence of individual parallel-bit words, the repetition rate of the data inside the burst being referred to as the “data rate”. When the data are received at the RAM (during writing operation) or at the controller (reading operation), the respective arriving data sequence is sampled at a frequency that is equal to the data rate. The strobe signal which is used for this purpose must be matched, not only in terms of its frequency but also in terms of its phase, to the clock of the received data in such a manner that the sampling times are, as much as possible, in the center of the bit periods and are not too close to the bit limits where reliable detection of the valid binary values is no longer guaranteed.
The higher the data rate, the more critical is the synchronization of the strobe signal for data sampling. Relatively recent SDRAMs operate at high data rates which are m times the system clock frequency, m being equal to 2 (i.e., double data rate or so-called DDR operation), 4, 8 or even higher. However, the data are written to, and read from, the memory cells at a slower rate (i.e., rate of the system clock), in each case in parallel to and from m different areas of the cell array, a 1/m multiplexer which is switched at the data rate being used in the SDRAM for the serial/parallel conversion of the data which have been received and for the parallel/serial conversion of the data which have been read, as is generally known.
In RAM/controller systems according to the prior art, a separate data clock signal is generated together with the respective transmission data at the respective transmitting end (controller in writing operation, RAM in writing operation), said data clock signal having a fixed phase relationship with the clock of the transmitted data and being transmitted to the receiving end in parallel with the data via a separate data clock line. This data clock line runs with the data lines in a common line bundle, with the result that virtually no (or only minimal) propagation time differences occur between the data and the data clock signal. At the receiving end, the strobe signal for sampling received data is derived from the received data clock signal.
FIG. 1 of the accompanying drawings schematically shows an example of the devices for synchronized signal transmission between an SDRAM and a controller according to the prior art mentioned above.
FIG. 1 shows parts of a conventional controller module 110 on the left-hand side and parts of a conventional SDRAM module 120 on the right beside said controller module. The two modules which are implemented as integrated circuits on separate chips are designed for reciprocal communication via transmission lines which are indicated by dashed lines in FIG. 1.
The SDRAM 120 shown in FIG. 1 has a plurality of signal connections for communicating with the controller 110, namely: a data connection D having n pins for receiving and transmitting data bursts DAT having a bit width of n from and to an identical data connection D′ of the controller 110 via a bundle of n parallel data lines DL; a synchronization signal connection S for receiving and transmitting a data clock signal DTS and DTS′ (which specifies the data clock) from and to an identical synchronization signal connection S′ of the controller 110 via a data clock line SL; an address input A having a plurality of pins for receiving an item of address information comprising a plurality of parallel bits ADR from an address output A′ of the controller 110 via a bundle of address lines AL; a command input B having a plurality of pins for receiving multibit command words BEF from a command output B′ of the controller 110 via a bundle of command lines BL; a clock input C for receiving a system clock signal CLK from a clock output C′ of the controller 110 via a system clock line C.
In order to synchronize the signals which are transmitted between the controller 110 and the SDRAM 120, transmission sampling circuits and reception sampling circuits are used at the respective connections. Each of these sampling circuits is designed in such a manner that, when a clock edge appears at its sampling control connection (strobe connection), it picks up the binary value of the signal present at the input and provides (“latches”) it at the output until the binary value which is then current is “latched” in the same manner with the next clock edge.
During the entire memory operation, the controller 110 transmits the system clock signal CLK, via a transmission amplifier CS and the system clock line CL, to the SDRAM 120 where said signal is amplified in a reception amplifier CE. In the controller 110, a command transmission sampling circuit BS and an address bit transmission sampling circuit AS are respectively used to synchronize the command bits BEF and the address bits ADR with the transmitted system clock signal CLK, and, in the SDRAM 120, a command reception sampling circuit BE and an address bit reception sampling circuit AE are respectively used to resynchronize said command bits and address bits with the system clock signal CLK which has been received there in order to correct any possible propagation time differences between the lines CL, BL and AL.
A command decoder 21 which is contained in the SDRAM 120 decodes the command bits BEF with synchronization by the received system clock signal CLK in order to stimulate individual command lines 22 for executing the respective commands, inter alia a command line AK for executing the activation command for initiating access to the memory cells of the SDRAM, command lines WD and RD for executing the write command (“Write Data”) and the read command (“Read Data”), and a command line IN for executing an initialization command at the beginning of memory operation. Stimulating the command line IN opens a mode register 23 for receiving information for setting certain mode parameters, for example the burst length (number of parallel data words in the data bursts) and the CAS latency (number of system clock periods for the waiting time between the activation command and the operation of writing to, or reading from, the memory cells of the SDRAM). The controller 110 applies this setting information, via the address input A of the SDRAM 120, to the mode register 23 during the initialization phase by switching certain address bits to the binary value “1”, said setting information causing certain “configuration bits” in this register to be set to “1” in order to provide a bit pattern that prescribes the mode parameters on configuration lines 24 during memory operation.
The memory cells of the SDRAM 120 are diagrammatically shown in FIG. 1 as a block 26, as is the control device 25 for write and read access to the memory cells. The access control device 25 receives the system clock signal CLK, the signals on the command lines 22 and the configuration bits in the mode register 23. The access control device 25 contains address decoders and a switchable network of data paths in order to control the writing of data to, and the reading of data from, the memory cells, as is generally known. Further parts of the SDRAM 120 and also of the controller 110 which interact when data is being transmitted between the two modules are described below in connection with writing operation and reading operation.
During operation, a transmission strobe signal SSS′ and SSS which is synchronized with CLK and whose clock edges appear at a repetition rate corresponding to the data rate is respectively generated in both modules 110 and 120 using a clock generator TG′ and TG.
Writing Operation:
The data to be written are retrieved at the data rate within the controller 110, for example from the data buffer of the controller (not shown). The data burst which has been retrieved is passed, via the data bus DB′, to the data input of a data transmission sampling circuit DS′ which samples the data using the transmission strobe signal SSS′. The write data in the controller 110 may likewise be retrieved using the transmission strobe signal SSS′ via a line 17. If necessary, a fixed delay may be inserted into said line 17 or into the data bus DB′ in order to ensure that the bit limits of the data at the data transmission sampling circuit DS′ are at a certain minimum distance from the edges of the strobe signal SSS′, and reliable sampling may thus be effected. The write data DAT′ which have been sampled are transmitted to the data connection D of the SDRAM 120 via the data lines DL.
In the case of the example shown, the accompanying data clock signal DTS′ which is likewise to be transmitted to the SDRAM 120 is generated in such a manner that its edges fall, as much as possible, in the center between the bit limits of the transmitted data. To this end, use is made of a separate transmission sampling circuit SS′ which receives a “simulated” bit sequence SBF′ which is generated in the controller 110 synchronously with the retrieved data and in which the two binary levels alternate between “0” and “1” from bit to bit. This bit sequence is sampled in the transmission sampling circuit SS′ using the strobe signal SSS′ in exactly the same way as the data in the transmission sampling circuit DS′ and is then delayed in a downstream delay element VG1 by an amount of time τ which is equal to half the period of the data rate. The data clock signal DTS′ obtained in this manner is transmitted to the synchronization signal connection S of the SDRAM 120 via the data clock line SL.
In the SDRAM 120, the data burst DAT′ which is received at the data connection D is passed to the input of a data reception sampling circuit DE where it is sampled using a reception strobe signal ESS. This signal ESS is derived from the received data clock signal DTS′, to be precise using a reception amplifier SE. On account of the delay τ (which has been inserted in the controller) in the data clock signal DTS′, the edges of the reception strobe signal ESS that is derived from the latter fall relatively precisely in the center between the bit limits of the data DAT′ received at the SDRAM 120. The data reception sampling circuit DE is designed in such a manner that it samples the received data both on the rising edge and on the falling edge of the reception strobe signal ESS. The circuit DE and also the data clock reception amplifier SE are switched on, only during writing operation, by means of a write state signal WRS which is rendered effective by the write command in the control device 25 of the SDRAM 120 and is rendered ineffective by the read command.
The reception data which are sampled in the data reception sampling circuit DE are passed, via the data bus DB, to the access control device 25, from where they are written to the memory cells selected by the address bits ADR.
Reading Operation:
The data which are read from the memory cells (selected by the address bits ADR) during reading operation are retrieved from a data buffer (not shown) in the access control device 25 of the SDRAM 120 at the data rate. The data burst which has been retrieved is passed, via the data bus DB, to the data input of a data transmission sampling circuit DS which samples the read data burst using the transmission strobe signal SSS. The read data may be retrieved via a line 27 using the transmission strobe signal SSS. If necessary, a fixed delay may be inserted into said line 27 or into the data bus DB in order to ensure that the bit limits of the data at the data transmission sampling circuit DS are at a certain minimum distance from the edges of the strobe signal SSS, and reliable sampling may thus be effected. The read data which have been sampled are transmitted to the data connection D′ of the controller 110 via the data lines DL.
In the case of the example shown, the accompanying data clock signal DTS which is likewise to be transmitted to the controller 110 is generated in such a manner that its edges coincide exactly with the bit limits of the transmitted data. To this end, use is also made, in the SDRAM 120, of a separate transmission sampling circuit SS which receives a simulated bit sequence SBF which is generated synchronously with the retrieved read data and in which the two binary levels alternate between “0” and “1” from bit to bit. This bit sequence is sampled in the transmission sampling circuit SS using the strobe signal SSS in exactly the same way as the data in the transmission sampling circuit DS of the SDRAM 120. The data clock signal DTS obtained in this manner is transmitted to the synchronization signal connection S′ of the controller 110 via the data clock line SL.
In the controller 110, the read data burst DAT received at the data connection D′ is passed to the input of a data reception sampling circuit DE′ where it is sampled using a reception strobe signal ESS′. This signal ESS′ is derived from the received data clock signal DTS, to be precise using a reception amplifier SE′ and a downstream delay element VG2 which gives rise to a delay by the amount of time τ, that is to say a delay by half the period of the data rate. The data reception sampling circuit DE′ is designed in such a manner that it samples the received read data burst both on the rising edge and on the falling edge of the reception strobe signal ESS′. The circuit DE′ and also the data clock reception amplifier SE′ are switched on, only during reading operation, by means of a read state signal RDS which is rendered effective in the controller 110 when the read command is sent and is rendered ineffective when the write command is sent.
The read data which have been sampled in the data reception sampling circuit DE′ of the controller 110 are forwarded, via the data bus DB′, for further processing.
As can be discerned from the explanations above, a bidirectional signal link for the data clock signals when writing and reading is required for data communication between a synchronous RAM and a controller in the prior art. Such a link requires a respective bidirectional port, that is to say an interface having means for changing over between transmission and reception operation, at both ends. In the example described, this interface respectively comprises a transmission sampling circuit SS and SS′ and a reception amplifier SE and SE′, wherein it is necessary to be able to switch the respective reception amplifier on and off in order to prevent the transmitted data clock signals from being transmitted back into the reception channel. This requires particular circuit and wiring complexity. Another problem with bidirectional signal links is the precise impedance and propagation time matching of the elements in the two interfaces. This matching is particularly important if the transmitted signals, like the data clock signals described, are used as a time base and therefore have to satisfy highly precise time criteria.